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1 document # sram135 rev or revised april 2007 description the p4c1298/l are a 262,144-bit ultra high speed static ram organized as 64k x 4. the cmos memory requires no clock or refreshing and has equal access and cycle times. inputs and outputs are fully ttl-compatible. the ram operates from a single 5v10% tolerance power supply. with battery backup, data integrity is maintained for supply voltages down to 2.0v. current drain is typically 10 a from a 2.0v supply. data retention with 2.0v supply three-state outputs ttl/cmos compatible outputs fully ttl compatible inputs standard pinout (jedec approved) ? 28-pin 300 mil dip, soj ? 28-pin 350x550 mil lcc features full cmos, 6t cell high speed (equal access and cycle times) ? 15/20/25/35 ns (commercial/industrial) ? 15/20/25/35/45 ns (military) low power single 5v10% power supply output enable & chip enable control functions functional block diagram pin configuration p4c1298/p4c1298l ultra high speed 64k x 4 static cmos ram access times as fast as 15 nanoseconds are available, permitting greatly enhanced system speeds. cmos is utilized to reduce power consumption. the p4c1298 is available in a 28-pin 300 mil dip or soj, as well as a 28-pin 350x500 mil lcc package, providing excellent board level densities. dip (p5, c5) soj (j5) lcc (l5)
p4c1298/l page 2 of 11 document # sram135 rev or maximum ratings (1) symbol parameter value unit v cc power supply pin with ?0.5 to +7 v respect to gnd terminal voltage with ?0.5 to v term respect to gnd v cc +0.5 v (up to 7.0v) t a operating temperature ?55 to +125 c symbol parameter value unit t bias temperature under ?55 to +125 c bias t stg storage temperature ?65 to +150 c p t power dissipation 1.0 w i out dc output current 50 ma recommended operating temperature and supply voltage industrial commercial grade(2) ambient temperature gnd v cc ?40c to +85c 0c to +70c 0v 0v 5.0v 10% 5.0v 10% symbol c in c out parameter input capacitance output capacitance conditions v in = 0v v out = 0v 5 7 unit pf pf capacitances (4) v cc = 5.0v, t a = 25c, f = 1.0mhz dc electrical characteristics over recommended operating temperature and supply voltage (2) notes: 1. stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to maximum rating conditions for extended periods may affect reliability. 2. extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. transient inputs with v il and i il not more negative than ?3.0v and ?100ma, respectively, are permissible for pulse widths up to 20 ns. 4. this parameter is sampled and not 100% tested. typ. i sb standby power supply current (ttl input levels) ce v ih v cc = max ., f = max., outputs open ___ 40 10 ma ma ___ ce v hc v cc = max., f = 0, outputs open v in v lc or v in v hc standby power supply current (cmos input levels) i sb1 symbol v ih v il v hc v lc v cd v ol v oh i li i lo parameter input high voltage input low voltage cmos input high voltage cmos input low voltage input clamp diode voltage output low voltage (ttl load) output high voltage (ttl load) input leakage current output leakage current test conditions v cc = min., i in = 18 ma i ol = +8 ma, v cc = min. i oh = ?4 ma, v cc = min. v cc = max. v in = gnd to v cc v cc = max., ce = v ih v out = gnd to v cc p4c1298 min 2.2 ?0.5 (3) v cc ?0.2 ?0.5 (3) 2.4 ?5 ?5 max v cc +0.5 0.8 v cc +0.5 0.2 ?1.2 0.4 +5 +5 unit v v v v v v v a a military -55c to +125c 0v 5.0v 10% ___ 20 10 ___ p4c1298l min 2.2 ?0.5 (3) v cc ?0.2 ?0.5 (3) 2.4 ?10 ?10 max v cc +0.5 0.8 v cc +0.5 0.2 ?1.2 0.4 +10 +10 ___ 20 ma ___ n/a mil ind/comm mil ind/comm 10 ma ___ n/a ___
p4c1298/l page 3 of 11 document # sram135 rev or *v cc = 5.5v. tested with outputs open. f = max. switching inputs are 0v and 3v. ce = v il data retention characteristics (p4c1298l only) symbol v dr i ccdr t cdr t r ? parameter v cc for data retention data retention current chip deselect to data retention time operation recovery time test conditions ce v cc ?0.2v, v in v cc ?0.2v or v in 0.2v min 2.0 0 t rc typ.* v cc = 2.0v 3.0v 10 15 max v cc = 2.0v 3.0v 1000 2000 unit v a ns ns data retention waveform *t a = +25c t rc = read cycle time ? this parameter is guaranteed but not tested. i cc symbol parameter temperature range dynamic operating current* commercial industrial ?15 ?20 ?25 ?35 unit ma ma power dissipation characteristics vs. speed 115 120 135 160 160 125 115 110 military ma 120 120 150 160
p4c1298/l page 4 of 11 document # sram135 rev or ac characteristics?read cycle (v cc = 5v 10%, all temperature ranges) (2) timing waveform of read cycle no. 2 (address controlled) (5,6) sym. t rc t aa t ac t oh t lz t hz t pu t pd parameter read cycle time address access time chip enable access time output hold from address change chip enable to output in low z chip disable to output in high z chip enable to power up time chip disable to power down time -15 min 15 3 3 0 max 15 15 8 15 -20 min 20 3 3 0 max 20 20 10 20 -25 min 25 3 3 0 max 25 25 15 25 -35 min 35 3 3 0 max 35 35 15 35 unit ns ns ns ns ns ns ns ns -45 min 45 3 3 0 max 45 45 20 45 t oe output enable low to data valid ns timing waveform of read cycle no. 1 ( oe oe oe oe oe controlled) (5) t olz t ohz output enable low to low z output enable high to high z 810152530 ns ns 0000 0 9 9 15 20 20
p4c1298/l page 5 of 11 document # sram135 rev or notes: 5. ce is low and we is high for read cycle. 6. we is high, and address must be valid prior to or coincident with ce transition low. 7. transition is measured 200mv from steady state voltage prior to change with specified loading in figure 1. this parameter is sampled and not 100% tested. 8. read cycle time is measured from the last valid address to the first transitioning address. timing waveform of read cycle no. 3 ( ce ce ce ce ce controlled) (5,6)
p4c1298/l page 6 of 11 document # sram135 rev or 12. write cycle time is measured from the last valid address to the first transition address. 13. transition is measured 200mv from steady state voltage prior to change with specified loading in figure 1. this parameter is sampled and not 100% tested. notes: 9. ce and we must be low for write cycle. 10. oe is low for this write cycle. 11. if ce goes high simultaneously with we high, the output remains in a high impedance state. timing waveform of write cycle no. 1 ( we we we we we controlled) (9) ac characteristics - write cycle (v cc = 5v 10%, all temperature ranges) (2) minmaxminmaxminmaxminmaxminmax t wc write cycle time 15 20 25 35 45 t cw chip enable time to end of write 10 15 20 25 30 t aw address valid to end of write 10 15 20 25 30 t as address set-up time 00000 t wp write pulse width 10 15 20 25 30 t ah address hold time from end of write 0 0 0 0 0 t dw data valid to end of write 9 10 15 20 20 t dh data hold time 00000 t wz write enable to output in high z 7 10 15 20 20 t ow output active from end of write 0 0 0 0 0 sym parameter -45 -15 -20 -25 -35
p4c1298/l page 7 of 11 document # sram135 rev or input pulse levels gnd to 3.0v input rise and fall times 3ns input timing reference level 1.5v output timing reference level 1.5v output load see figures 1 and 2 mode ce ce ce ce ce we we we we we output power standby h x high z standby read l h d out active write l l d in active * including scope and test fixture. note: because of the ultra-high speed of the p4c1298, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. long high-inductance leads that cause supply bounce must be avoided by bringing the v cc and ground planes directly up to the contactor fingers. a 0.01 f high frequency capacitor is also required between v cc and ground. to avoid signal reflections, proper termination must be used; for example, a 50 ? test environment should be terminated into a 50 ? load with 1.73v (thevenin voltage) at the comparator input, and a 116 ? resistor must be used in series with d out to match 166 ? (thevenin resistance). figure 1. output load figure 2. thevenin equivalent ac test conditions truth table timing waveform of write cycle no. 2 ( ce ce ce ce ce controlled) (9,10)
p4c1298/l page 8 of 11 document # sram135 rev or ordering information 1513 10 selection guide the p4c1298 is available in the following temperature, speed and package options. 15 20 25 35 commercial plastic soj, 300 mil -15j3c -20j3c -25j3c -35j3c industrial plastic soj, 300 mil -15j3i -20j3i -25j3i -35j3i ceramic dip, 300 mil -15cm -20cm -25cm -35cm 28-pin ceramic lcc -15l28m -20l28m -25l28m -25l28m ceramic dip, 300 mil -15cmb -20cmb -25cmb -35cmb 28-pin ceramic lcc -15l28mb -20l28mb -25l28mb -25l28mb speed military temperature military processeed* temperature range package
p4c1298/l page 9 of 11 document # sram135 rev or soj small outline ic package plastic dual in-line package pkg # # pins symbol min max a 0.120 0.148 a1 0.078 - b 0.014 0.020 c 0.007 0.011 d 0.700 0.730 e e e1 0.292 0.300 e2 q0.025- j5 28 (300 mil) 0.050 bsc 0.267 bsc 0.335 bsc pkg # # pins symbol min max a - 0.210 a1 - b 0.014 0.023 b2 0.045 0.070 c 0.008 0.014 d 1.345 1.400 e1 0.270 0.300 e 0.300 0.380 e eb - 0.430 l 0.115 0.150 0 15 0.100 bsc p5 28 (300 mil)
p4c1298/l page 10 of 11 document # sram135 rev or rectangular leadless chip carrier sidebrazed dual in-line package pkg # # pins symbol min max a 0.060 0.075 a1 0.050 0.065 b1 0.022 0.028 d 0.342 0.358 d1 d2 d3 - 0.358 e 0.540 0.560 e1 e2 e3 - 0.558 e h j l 0.045 0.055 l1 0.045 0.055 l2 0.075 0.095 nd ne 0.020 ref 5 9 0.400 bsc 0.200 bsc 0.050 bsc 0.040 ref l5 28 0.200 bsc 0.100 bsc pkg # # pins symbol min max a-0.225 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 d-1.485 e 0.240 0.310 ea e l 0.125 0.200 q 0.015 0.070 s1 0.005 - s2 0.005 - c5 28 (300 mil) 0.300 bsc 0.100 bsc
p4c1298/l page 11 of 11 document # sram135 rev or revisions document number : sram135 document title : p4c1298/p4c1298l ultra high speed 64k x 4 static cmos ram rev. issue date orig. of change description of change or apr-07 jdb new data sheet

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